- Error elimination and stability improvement for OCZ3X16002G SPD
Memory modules from OCZ Technology are produced with a very poor SPD firmware.
Sometimes it does not comply with official JEDEC standards and recommendations.
This tutorial will describe some useful tricks on how to fix the lacks in SPD of
the OCZ OCZ3X16004GK DDR3 SDRAM memory retail kit.
First of all, clink on the Report button to see the memory timings.
As you can see, the timing configuration table is incorrectly defined because of
some SPD errors made by OCZ’s engineers while having fun with an OEM SPD firmware from
Micron Technology. The main clock frequency of 667MHz is listed two times! Besides, the main timings such as tCL, tRCD, tRP, tRAS, etc
do not meet JEDEC requirements specific for DDR3-1333. We will get them back
again to recommended values.
To correct the timing configuration table call Timing Table Editor by pressing F9
key or by clicking on the
Editor button on the main toolbar. A new window will appear as follows.
As you probably know, all proper DDR3-1333 RAM sticks have a recommended CAS
Latency of 9T. Now look at the
Max CAS field! It has 7T what is a wrong value. To fix this error select
108 from the Min CAS Latency Time dropped down box. This will also
tAA Min parameter to recommended 13.50 ns. Then click Next and
choose the "Update Hex Editor with new SPD data" option. Click Apply
to save changes you have just made with SPD. Now switch Thaiphoon Burner to the
Report mode again and look at the new timing table.
Well done! It is correct now, but not completely yet. Now we are going to remove
CAS Latency of 5T and 7T as these values are not recommended for DDR3-1333 SPD.
Call Timing Table Editor once again. Locate the CAS Latencies dropped down
box in the DRAM Timing Delays Group. Now choose 5T from this box and
click on Supported to uncheck it. Select 7T and uncheck the Supported
checkbox once again. Now apply SPD changes like in the previous step and switch
Thaiphoon Burner to the Report mode again.
Great! We have just removed non-recommended CAS Latencies! Thanks to Timing Table
Editor that was easy!
So, what is next? Now, we are going to restore some of the memory timings to
their standard values. Call Timing Table Editor and change values of dropped
down boxes of the DRAM Timing Delays Group in accordance with the
OK. Now apply changes and click Report to check your new timing configuration table. It should look like on the next screenshot.
The final step is CRC fixing. Turn on Write Protection Mode by pushing the Protect button. Now choose the Correct Checksum command from the EEPROM main menu. Confirm suggestions to fix CRC in the next dialog box.
Original OCZ3X16002G SPD firmware
Improved OCZ3X16002G SPD firmware