January 4, 2018

Thaiphoon Burner Super Blaster has been released. A list of then new features is below.

  • Part Number of SpecTek DRAM components is displayed and build in accordance with Micron’s Part Numbering;
  • Part Number of Hynix DDR2 components is displayed and built in accordance with legacy and new Hynix rules;
  • Attached DDR3 DRAM part numbering system of Elpida Memory to build DRAM part numbers;
  • Attached the latest part numbering system of Nanya Technology for DDR4 8Gb A-die components;
  • Added building part numbers for Qimonda DDR2 DRAM components;
  • A simple process manager has been developed to prevent SPD data from corruption and inconsistency while reading EEPROM. Before reading SPD EEPROM content the program enumerates all running processes to find ones related to temperature and RGB LED control software, e.g. ASUS Aura Sync based applications. When found, the list of all unsafe processes is displayed. The user can terminate them or ignore the warning;
  • Module Series is displayed in the summary and full reports for G.SKILL, Corsair, GoodRAM, AMD and Crucial DRAM modules;
  • A huge improvement in building part numbers and die identification of DDR, DDR2 and DDR3 DRAM components has been made. If this data is not found in SPD bytes the alternative function is called for analyzing the part number of memory modules to determine the manufacturer and die generation of used DRAM components. This functions works perfectly for memory modules manufactured by Apacer, ASint, Crucial, Ramaxel, RAmos, Kingmax, Swissbit, Smart Modular and others;
  • The SPD Browser can fetch SPD dumps from SPD database by DRAM Manufacturer criteria. Besides, after updating the SPD database file the user can browse the recently added SPD dumps immediately or by executing “NEW” search query lately;
  • The Comparator tool provides reading SPD EEPROM content to the right HEX panel which is defined for reference purposes. This improvement lets the user compare SPDs of their modules quick and easy;
  • Used a PageControl component to switch between the three modes of Welcome Screen, Full Summary/Report and HEX. Such an interface design concept makes UI more responsive and takes less time to redraw the interface itself;
  • SPD reading/writing is performed two times faster for 4-Kbit DDR4 EEPROM devices;
  • The new efficient programming algorithm for Intel SMBus Host Controllers enables to read SPD EEPROM data 14 times faster. Now it takes about 500 milliseconds to complete reading of 512 SPD bytes.

April 5, 2018

Thaiphoon Burner Super Blaster has been released. Below is the list of new features.

  • The new Timing Table Editor for DDR2 SPD has been developed. It has an in-depth interface design implementation that allows editing all the necessary memory timings of SPD intuitively.
  • Every editing tool now has a navigation bar in one color style and minimum set of control buttons. The color of the navigation bar is customized in the Settings menu.
  • The procedure for analyzing Part Numbers of memory modules now supports the DDR4 Part Numbering system of Smart Modular. This helps to determine DRAM Manufacturer and DRAM Die if these two required parameters were not programmed in SPD.
  • To comply with the “JEDEC SPD for DDR4 Release 3 Annex” the Timing Table Editor sets the Maximum DRAM Cycle Time to 1.6 ns (625 MHz) for every preset of the JEDEC standard speed bin list.
  • The SPDWD Patch Assistant enables to select the PCIEXBAR address from the list, which is filled with the three base addresses being most typical for the Intel platform.
  • Added description for all the SPD bytes of DDR4 LRDIMM being displayed on the Statusbar.
  • SPD release dates of DDR4 DRAM modules have been revised.
  • The “Product Details” Editor sets the Odd Parity bit in all the Manufacturer ID Codes to meet JEDEC requirements.
  • Added SMBus Controller Device ID of Intel Gemini Lake code-named SOCs to enable accessing SPD EEPROM.
  • The part marking of Hynix DDR2 SDRAM components, mounted on the third-party DRAM modules, is determined.
  • The full report includes detailed information specific to hybrid DDR4 NVDIMM modules.
  • The SPD Browser enables to fetch SPD dumps from the SPD database by “NVDIMM” module type.
  • Fixed a bug due to the Register Manufacturer and Register Model fields not being displayed for DDR4 NVRDIMM and DDR4 LRDIMM.
  • Fixed a bug due SPD data not being decoded when opening the SPD dump from the database if the “Add to shortcuts” button has been pressed before.
  • Fixed “Division by zero” error due to SPD reporting not being possible for certain DRAM module manufacturers.

June 1, 2018

Thaiphoon Burner Super Blaster has been released. It is a non-planned version with the special improvements for the AMD Family 17h processors.

  • Fixed a bug due to the Maximum Clock Cycle Time of the Timing Table Editor for DDR2 SPD not being correctly set and displayed;
  • The SPD Generator has been improved. The new “DIMM Thermal Sensor” checkbox has been added. Various SPD bytes are additionally set in accordance with JEDEC SPD4 annexes for UDIMM and RDIMM;
  • The Product Details editor has two extra dropped-down listboxes specific for DDR3 and DDR4 registered DRAM modules;
  • Added preliminary identification of Micron’s new generation DDR4 8-Gbit 1ynm J-die DRAM components with Design ID Z21C;
  • The Micron Technology DDR2 Part Numbering system has been attached to build and display markings for single-die and some of dual-die DRAM components;
  • The “Bright Gray” color scheme has been changed and renamed to “Native”;
  • A new efficient SMBus Controller programming algorithm has been used for AMD systems. It performs SPD reading 40 times faster. Now it takes about 0.20 seconds to complete reading a 512-Kbit SPD EEPROM;
  • The XMP Enhancer is capable of reading the Timing register sets of the AMD Family 10h processors (AMD Ryzen 1000 series, AMD Ryzen 2000 series and AMD Epyc). This enables to create XMP profiles on the base of the current DRAM timings. It is possible to read DRAM timings from two DRAM controllers independently;
  • The “DRAM Controller Status” viewer is a new powerful addition that was designed to check various parameters and the current DRAM timings of the AMD Family 17h processors.

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